1. Field of the Invention
The present invention relates to a super high-speed sequential column decoder which adjusts a delay degree during a burst operation in a clock synchronous memory. More particularly, it relates to a super high-speed sequential column decoder which generates high-speed successive output signals by using a pipe lining method, and is, thus, operated irrespective of an applied speed of an external input clock signal.
2. Description of the Prior Art
In general, when a synchronous memory synchronized by an external input clock signal performs a burst operation, each column decoder's output is generated with an always synchronized clock signal. Accordingly, the time from an external clock signal to a column decoder output, which loads a bit-line data of a bit-line sense amplifier on a data bus line, becomes longer, wherein a bottle neck phenomenon occurs in the high-speed operation.
FIG. 1 is a circuit diagram of a conventional column decoder in which a burst-length is set to `4`.
Referring to FIG. 1, the conventional column decoder includes:
a column address decoding portion 100 which receives a plurality of predecoding signals of a column address as an input, decodes the signals, and transmits a plurality of decoding signals S0-S3 to a driving portion 200; and a driving portion 200 which receives the decoding signals S0-S3 as an input, is synchronized by a clock signal, and generates a plurality of column decoding signals CDijk.sub.-- 0-CDijk.sub.-- 3.
The column address decoding portion 100 includes:
three-input NAND gates NAND1-NAND4 which receive predecoding signals YAi.sub.-- 0-YAi.sub.-- 3 of a column address as a first input, and receive predecoding signals YAj.sub.-- n and YAk.sub.-- n of another column address as second and third inputs; and a plurality of buffering inverters I1-I8 which are connected to output nodes of the NAND gates NAND1-NAND4.
The driving portion 200 includes a plurality of inverters I9-I12 which receive the output signals S0-S3 of the column address decoding portion 100.
Although the present invention employs a structure used for a case of a burst-length `4` as an example, it can embody other case of burst-length `2` and `8`, and a full page case of a burst-length `16` by using the same structure.
The signals YAi.sub.-- 0-YAi.sub.-- 3 which are input signals of the above column decoder can be an external input column address, and may be a predecoding signal of a column address generated by an internal counter.
However, since the signals YAi.sub.-- 0-YAi.sub.-- 3 are generated after being synchronized by a clock signal, their output signals CDijk.sub.-- 0-CDijk.sub.-- 3 are generated after being synchronized by the clock signal. Accordingly, a memory performing a sequential burst operation has a time limit in a high-speed burst operation.
FIG. 2 is a timing diagram of a burst operation of a conventional clock synchronous memory. Referring to FIG. 2, (a)CLK indicates an external input clock signal, (b)int.sub.-- CLK indicates a clock signal generated in the inside of the conventional clock synchronous memory, (c)Y-ADDR indicates a column address signal, and (d)CDijk.sub.-- 0-CDijk.sub.-- 3 indicate each output signal of a column decoder.
In addition, i, j, and k indicate a predecoding combination of addresses.
As shown in FIG. 2, when performing a sequential burst operation, the conventional column decoder is synchronized by an external clock signal CLK, and sequentially generates four column decoder signals CDijk.sub.-- 0-CDijk.sub.-- 3 because of a burst-length `4`. Therefore, as a frequency of the external clock signal CLK rises, a time delay problem in a mutual communication line according to a circuit configuration or fabrication technique for producing the column decoder signal becomes serious.